1. Field of the Invention
The present invention relates to a single-poly electrically-erasable programmable read-only-memory (EEPROM) cell and, more particularly, to a single-poly EEPROM cell that is programmable and erasable in a low-voltage environment.
2. Description of the Related Art
A single-poly electrically-programmable read-only-memory (EPROM) cell is a non-volatile storage device which is fabricated using process steps that are fully compatible with conventional single-poly CMOS fabrication process steps. As a result, single-poly EPROM cells are often embedded in CMOS logic and mixed-signal circuits.
FIGS. 1A-1C show a series of views that illustrate a conventional single-poly EPROM cell 100. FIG. 1A shows a plan view of cell 100, FIG. 1B shows a cross-sectional view taken along line 1B--1B of FIG. 1A, while FIG. 1C shows a cross-sectional view taken along line 1C--1C of FIG. 1A.
As shown in FIGS. 1A-1C, EPROM cell 100 includes spaced-apart source and drain regions 114 and 116, respectively, which are formed in a p-type semiconductor material 112, such as a well or a substrate, and a channel region 118 which is defined between source and drain regions 114 and 116.
As further shown in FIGS. 1A-1C, cell 100 also includes an n-well 120 which is formed in p-type material 112, and a field oxide region FOX which is formed in p-type material 112 to isolate source region 114, drain region 116, and channel region 118 from n-well 120.
In addition, cell 100 further includes adjoining p+ and n+ contact regions 122 and 124, respectively, which are formed in n-well 120. Current generation cells also include a p-type lightly-doped-drain (PLDD) region 126 which adjoins p+ contact region 122.
Further, a control gate region 128 is defined between PLDD region 126 and the field oxide region FOX that isolates n-well 120 from source region 114, drain region 116, and channel region 118. In addition, a layer of gate oxide 130 is formed over channel region 118, a layer of control gate oxide 132 is formed over control gate region 128, and a floating gate 134 is formed over gate oxide layer 130, control gate oxide layer 132, and a portion of the field oxide region FOX.
During the fabrication of cell 100, gate oxide layer 130 and control gate oxide layer 132 are typically grown at the same time and, as a result, have substantially the same thickness, e.g. approximately 120 .ANG. for 0.5 micron technology, and 70 .ANG. for 0.35 micron technology.
In operation, cell 100 is programmed by applying approximately 12 volts to contact regions 122 and 124, which are shorted together, and approximately 6-7 volts to drain region 116. In addition, both p-type material 112 and source region 114 are grounded.
When the positive voltage is applied to contacts 122 and 124, a positive potential is induced on floating gate 134. Specifically, the positive voltage applied to n+ contact region 124 in conjunction with the potential of floating gate 134 forms a deep depletion region at the surface of control gate region 128 which, in turn, reduces the potential at the surface of control gate region 128.
The positive voltage applied to p+ contact region 122 slightly forward-biases the p+ contact region to n-well junction at the surface of control gate region 128. As a result, holes are injected into the surface region of control gate region 128, thereby inverting the surface of control gate region 128.
The injected holes quickly (in picoseconds) reduce the depth of the depletion region at the surface of control gate region 128 which, in turn, places substantially all of the voltage applied to contact region 124 across control gate oxide layer 132. As a result, the initial potential induced on floating gate 134 is defined by the voltage applied to contact regions 122 and 124, and the thickness of control gate oxide layer 132 (which defines the coupling ratio between n-well 120 and floating gate 134).
Without the presence of p+ contact region 122, few holes would accumulate at the surface of control gate region 128 when the surface is initially depleted because n-well 120 contains relatively few holes. Thus, the depth of the depletion region can only be slowly reduced in size as thermally-generated holes drift up to the surface of control gate region 128.
Since the depth of the depletion region is initially large, the initial potential induced on floating gate 134 is substantially less because the voltage applied to contact 124 is placed across both control gate oxide layer 132 and a relatively large depletion region. Thus, p+ region 122 provides a method for quickly reducing the depth of the depletion region after the surface of control gate region 128 is depleted which, in turn, increases the potential initially induced on floating gate 134.
As noted above, current generation cells also require the use of PLDD region 126. As is well known, the thickness of control gate oxide layer 132 at the edge of the layer which is adjacent to p+ contact region 122 is slightly thicker than the central portion of the layer due to the well-known process step of re-oxidation after the poly gate has been etched. As a result, the depletion region formed at the edge is too small to sufficiently invert the surface which, in turn, limits the ability of p+ contact region 122 to inject holes into the surface of control gate region 128.
Thus, current generation cells utilize PLDD region 126 to form a hole injection region that adjoins the surface region of control gate region 128 away from the edge. Previous generation cells did not require a PLDD region because the thermal steps used during the fabrication of these cells allowed sufficient lateral diffusion of p+ contact region 122.
Returning again to the operation of cell 100, the positive potential induced on floating gate 134 from the application of a positive voltage to contact regions 122 and 124 forms a depletion region in channel region 118 which increases the potential at the surface of channel region 118. Source region 114 then injects electrons into the surface of channel region 118 which, in turn, forms a channel of mobile electrons.
The positive voltage applied to drain region 116 sets up an electric field between source and drain regions 114 and 116 which then accelerates the electrons in the channel. The accelerated electrons then have ionizing collisions that form "channel hot electrons". The positive potential of floating gate 134 attracts these channel hot electrons which penetrate gate oxide layer 130 and begin accumulating on floating gate 134, thereby raising the threshold voltage of cell 100.
Cell 100 is read by applying approximately 5 volts to contact regions 122 and 124, and approximately 1-2 volts to drain region 116. In addition, both p-type material 112 and source region 114 are grounded.
Under these bias conditions, a positive potential is induced on floating gate 134 by the above-described mechanism which is sufficient, i.e., larger than the threshold voltage of the cell, to create a channel current that flows from drain region 116 to source region 114 if cell 100 has not been programmed, and insufficient, i.e., less than the threshold voltage of the cell, to create the channel current if cell 100 has been programmed. The logic state of cell 100 is then determined by comparing the magnitude of the channel current flowing into drain region 116 with a reference current.
EPROM cell 100 is erased by irradiating cell 100 with ultraviolet (UV) light to remove the electrons. The UV light increases the energy of the electrons which, in turn, allows the electrons to penetrate the surrounding layers of oxide.
One problem with single-poly EPROM cells that are embedded in CMOS logic and mixed-signal circuits is that the cells are not well suited for low-voltage and low-power applications. Thus, when the underlying circuitry is scaled down for low-power applications, single-poly EPROM cells still require high-voltage circuitry to provide the needed programming voltages.
In addition, the formation of channel hot electrons during the programming of a conventional single-poly EPROM cell draws a relatively large current for low-power applications. Thus, there is a need for a single-poly EPROM cell that operates in a low-voltage environment.
The invention of the parent application provided a single-poly EPROM cell that was programmable in a low-voltage environment. There still remains, however, a need for a single-poly electrically-erasable programmable read-only-memory (EEPROM) cell that can be both programmed and erased in a low-voltage environment.